1. Field
The present invention relates generally to electronics circuits, and more specifically to a digital phase-locked loop (PLL).
2. Background
Phase-locked loops are an integral part of many electronics circuits and are particularly important in communication circuits. For example, digital systems use clock signals to trigger synchronous circuits (e.g., flip-flops). Transmitter and receiver systems use local oscillator (LO) signals for frequency upconversion and downconversion, respectively. Wireless devices (e.g., cellular phones) in wireless communication systems typically use clock signals for digital circuitry and LO signals for transmitter and receiver circuitry. Clock and LO signals are often generated with phase-locked loops.
FIG. 1 shows a classical PLL 100, which consists of a phase frequency detector (PFD) 110, a loop filter 120, a voltage controlled oscillator (VCO) 140, and a divider 150. VCO 140 generates an oscillator signal having a frequency determined by a control signal from loop filter 120. Divider 150 divides the oscillator signal in frequency by a factor of N, where N≧1, and provides a feedback signal. Phase frequency detector 110 receives a reference signal and the feedback signal, compares the phases of the two signals, and provides a detector signal that is proportional to the detected phase difference or error between the two signals. Loop filter 120 filters the detector signal and provides the control signal for VCO 140. Loop filter 120 adjusts the control signal such that the phase of the feedback signal is locked to that of the reference signal.
For an analog PLL, the loop filter is implemented with analog circuit components (e.g., capacitors and resistors). An analog PLL design is prone to various disadvantages such as a large die area for the loop filter (which can occupy as much as 50% of the total area of the PLL), significant noise coupling through the substrate for a system-on-a-chip (SOC) design, and large spurs in the oscillator signal due to gate leakage. Gate leakage increases exponentially with the reduction in oxide thickness and is thus more problematic as integrated circuit (IC) technology scales smaller.
A digital PLL avoids the disadvantages described above for the analog PLL. However, a major challenge for a digital PLL design is obtaining a wide closed loop bandwidth while maintaining high frequency resolution. Wide loop bandwidth is desired for better tracking of the reference signal, which then reduces the amount of phase noise generated by the VCO and results in lower jitter. Jitter is the deviation from the average or expected cycle of the reference signal. High frequency resolution is desired to reduce jitter. The limitation in frequency resolution results from coarse quantization of the phase error with a high frequency signal, such as the oscillator signal. In one conventional method, improved frequency resolution is achieved by taking more phase measurements before updating the loop filter. However, this method severely limits the achievable closed loop bandwidth (which then impacts jitter) and further introduces a large loop delay that degrades stability.
There is therefore a need in the art for a digital PLL with improved performance.